I have devoted my eighteen-year career to developing, analyzing,
and bringing new technologies to market – as an engineer, inventor, and
business leader. After graduating from MIT, and prior to joining Stanford’s
Graduate School of Business as a Sloan Fellow, I patented more than a dozen
of my own inventions, worked as a senior engineer developing hardware and
software, joined tiger-team groups at large companies on mission-critical
projects, and founded and ran several high technology startup companies. I
have marketed, negotiated, and closed numerous licensing agreements exceeding
one million dollars with large public companies (Cisco, Fujitsu, and Siemens)
related to software and intellectual property rights. I offer an unusual
blend of technical, quantitative, and interpersonal skills for discovering, analyzing,
managing and investing in technology start-ups.
Education
Stanford University Graduate School of Business Stanford, CA
Master of Science in Management (Sloan Program), 2007
Emphasis on Entrepreneurship, Venture Capital,
Leadership, Distressed Debt and Debt Markets
3rd Place Winner of BASES E-Challenge (of 110),
Entrepreneur, Venture-Capital, and High-Tech Clubs
Stanford University Stanford, CA
Postgraduate courses: 1991 - 1993
Advanced Computer Organization, Computer Graphics,
Statistics, Digital Communication Theory, Information Theory, Advanced
Information Theory.
Massachusetts Institute of Technology Cambridge, MA
Master of Science: Electrical Engineering and Computer
Science, June 1990.
Massachusetts Institute of Technology Cambridge, MA
Bachelor of Science: Electrical Engineering, June 1990.
Concentration: Digital Signal Processing; Telephony, Speech
Recognition; Competitive Decision Making
Experience
Enounce, Incorporated Palo Alto, CA
President and Chairman of the Board 1999-Present
Founded and incorporated company in 1998. Developed
company\'s patent portfolio, technology direction, and strategic
relationships. Recruited "dream-team" of technical experts in
digital media fields. Pioneered sales approaches and grew revenues from
existing software library while company developed next generation products.
Responsible for general infrastructure development: legal, capital,
computing, marketing, and sales. Inventor on ten patent applications. Raised
3/4 million dollars for Company\'s initial financing. Negotiated
reverse-triangle merger acquisition with publicly traded company that was not
consummated. Navigated company through dot.com downturn and achieved
profitability.
MXGO Technologies Incorporated Santa Clara, CA
Vice President of Business Development, Founder 2006-Present
Business development and IP monetization strategy for
patented email technology.
Forte Design Systems (Formerly CynApps, Inc) Santa Clara, CA
Director of Applications Engineering, Founder 1998-1999
Created marketing materials, and developed early adopters’
relationships. Grew applications group, coordinated seed customer trials,
and built company computing infrastructure. Leveraged knowledge of Verilog and
C++ to help define C++ class extensions. Recruited and managed application
engineering staff.
Experience
Ambit Design Systems, Inc. (Acquired by Cadence for
$250M) Santa Clara, CA
First Application Engineer (tenth employee): Early
responsibilities included product testing, acquiring customer designs,
scheduling and tracking of Product Releases, prioritization of features,
early testing, bug tracking, and verification using customer databases and
designs. Proactively participated in OVI / IEEE 1364.1 standards meetings for
synthesis. Recruited Application Engineers, developed "Rules of
Engagement" for evaluations, authored published technical papers.
Synthesized first "Large (775K/250K) Production" ASIC at Cisco
Systems using LSI G10p, handled back-end IPO work, etc. Worked with other
groups at company to grow a user community and helped drive product use on 3
production ASICs.
Verification Consulting Services (Cisco, Firepower, HP) Los Altos, CA
Consultant, Board Member, Founder 1995
Consulting in ASIC Design Verification, Test
methodologies, and CAD environments using Verilog. Projects include: MP cache
architectures for PowerPC processor, ATM switch controllers and multicast
engines. Clients included Cisco Systems, Firepower. Taught
"Verilog" courses at HP.
Chronologic Simulation Los Altos, CA
Technical Account Manager 1994
- 1995
Evaluated and proposed improvements for CAD flows
utilizing VCS and VMC. Gave technical presentations on alternative CAD
methodologies and Verilog coding styles. Wrote technical "white
papers" for new products. Technical support of VMC product line and
resolution of VCS product issues (including race conditions, PLI,
compilation) for Western region and major accounts nationwide.
Independent Contractor (NVidia) Mountain View, CA
Technical Consultant / Instructor 1994
Software and ASIC design work (including C-model
integration via PLI and test vector extraction and synthesis verification)
for NVidia.
Qualcomm Inc., Systems Engineering Group San Diego, CA
Systems Engineer 1993
- 1994
Analyzed, simulated and explored alternative system design
for Forward-Link of GlobalStar (Satellite CDMA cellular telephone/data
network) Modeled theoretical optimum and evaluated impact of design
trade-offs for ASIC implementations. Simulation was based on IS-95 waveform
with satellite channel model, and various tracking loops. Approximately 10K
lines of code in C and C++.
Sun Microsystems Inc., Desktop Graphics Development Mountain View, CA
Graphics Accelerator Chip Design: One of five hardware
design engineers who developed the graphics accelerator/vector processor
memory controller for the SparcStation 10 and 20 workstations. Verilog
hardware design and CAD flow, software performance analysis and simulation
Memory Display Interface: One of three hardware engineers.
Coded a functional hardware simulator in C for design verification. Developed
and managed design environment and CAD flow.
ROLM Systems Incorporated - IBM/Siemens Santa Clara, CA
Graduate Researcher June
1989 - December 1989
Designed and implemented a time-scale modification
algorithm for speech in C and assembly code for signal processing chip.
Analyzed and improved algorithm efficiency and quality for real-time
telephony applications, then developed improved algorithm (US Patent
5,175,769). The completed project produced high-quality, natural-sounding
speech at increased or decreased speaking rates.
Patents
Germany 69230324.3; United Kingdom 0525544, France 0525544, Italy 0525544,
US 5,175,769: Method and
Apparatus for Time-Scale Modification of Signals
US 5,287,508: Method and
Apparatus for Efficient Scheduling in a Multiprocessor Environment
US 6,266,674: Random Access
Information Retrieval Utilizing User-Defined Labels
US 6,370,688:Method
and Apparatus for Server Broadcast of Time-Converging Multi-Media Streams
US 6,374,225: Method and
Apparatus to Prepare Listener-Interest-Filtered Works
US 6,598,228:Method and Apparatus for Controlling Time-Scale
Modification During Multi-Media Broadcasts
US 6,625,655:Method and
Apparatus for Providing Continuous Playback or Distribution of Audio and
Audio-Visual Streamed Multimedia Received Over Networks Having
Non-Deterministic Delays
US 6,625,656:Method and
Apparatus for Continuous Playback or Distribution of Information Including
Audio-Visual Streamed Multimedia
US 6,801,888:Method and
Apparatus to Determine and Use Audience Affinity and Aptitude
US 6,934,759:Method and
Apparatus for User-Time-Alignment for Broadcast Works
US 7,043,433:Method and
Apparatus to Determine and Use Audience Affinity and Aptitude
US 7,100,188:Method and
Apparatus for Controlling Time-Scale Modification During Multi-Media Broadcasts
US 7,299,184: Method and
Apparatus to Prepare Listener-Interest-Filtered Works
Publications
An Integrated Environment
for Concurrent Development of a Pixel Processor ASIC and Application
Software. International Conference on Computer Design, 1993. Boston, MA.
The Architecture of an
Integrated Graphics Accelerator. International Conference on Computer Design,
1993. Boston, MA.
"Using Ambit\'s
BuildGates to Time and Synthesize Interfaces Involving Multiple Clock Domains
and Complex Inter-Clock Relationships", Design Wave Magazine #12, Japan, 1997.
IEEE 1364.1 Standards
Committee Draft on Synthesizable subset for Verilog Description Language.
Technical Analytical
Skills
·Inventive approach to technological problems, often generating
new solutions and patents.
·Financial Modeling: Pro Forma forecasting, valuation, and cash
flow analysis
·Statistical Analysis: Data Regression, linear and non-linear
optimization
·Extensive experience programming in C, C++, PASCAL, SCHEME,
ELISP, PERL, Tcl, Makefiles, C-shell, and Bourne shell. Minor programming in
Java, PHP, SQL, Visual Basic, and MFC.
·Hardware Design and behavioral modeling using VERILOG/Synopsys
(including PLI).
·Experience developing three production ASICs with Synopsys and
LSI design tools for CAD flow of VLSI development.
Photonix
